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  Datasheet File OCR Text:
 HCTS109T
Data Sheet July 1999 File Number
4624.1
Radiation Hardened Dual JK Flip Flop
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS109T is a Radiation Hardened Dual JK Flip Flop with set and reset. The flip flop changes state with the positive transition of the clock (CP1 or CP2).
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) * 3 Micron Radiation Hardened SOS CMOS * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * LSTTL Input Logic Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min * Input Current Levels Ii 5mA at VOL, VOH
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HCTS109T are contained in SMD 5962-95769. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
Pinouts
HCTS109T (SBDIP), CDIP2-T16 TOP VIEW
RI J1 K1 1 2 3 4 5 6 7 8 16 VCC 15 R2 14 J2 13 K2 12 CP2 11 S2 10 Q2 9 Q2
Ordering Information
ORDERING NUMBER 5962R9576901TEC 5962R9576901TXC PART NUMBER HCTS109DTR HCTS109KTR TEMP. RANGE (oC) -55 to 125 -55 to 125
CP1 S1 Q1 Q1 GND
NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct.
R1 J1 K1 CP1 S1 Q1 Q1 GND
HCTS109T (FLATPACK), CDFP4-F16 TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC R2 J2 K2 CP2 S2 Q2 Q2
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS109T Functional Diagram
5 (11) S 2 (14) J 3 (13) K 4 (12) CP 1 (15) R 16 VCC 8 GND 6 (10) Q 7 (9) Q Q
J
S F/F
Q
K
CL CL R
TRUTH TABLE INPUTS S L H L H H H H H R H L L H H H H H L CP X X X J X X X L H L H X K X X X L L H H X H No Change Q H L H L Toggle No Change L OUTPUTS Q L H H H
Unpredictable and unstable condition if both S and R go high simultaneously.
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HCTS109T Die Characteristics
DIE DIMENSIONS: 2261m x 2235m x 533m 51m) 89 x 88 x 21mils 2mil METALLIZATION: Type: Al Si Thickness: 11kA 1kA SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO2) Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 268 PROCESS: CMOS SOS
Metallization Mask Layout
HCTS109T
J1 (2) R1 (1) VCC (16)
K1 (3)
(15) R2
CP1 (4)
(14) J2
S1 (5) (13) K2
Q1 (6)
(12) CP2
(11) S2 Q1 (7)
(8) GND
(9) Q2
(10) Q2
NOTE: The die diagram is a generic plot form a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS109 is TA14440A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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